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L4969
SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT LOW SPEED CAN-TRANSCEIVER
PRELIMINARY DATA
s s s
s
s s s
s s
OPERATING SUPPLY VOLTAGE 6V TO 28V, TRANSIENT UP TO 40V LOW QUIESCENT CURRENT CONSUMPTION, LESS THAN 40A IN SLEEP MODE TWO VERY LOW DROP VOLTAGE REGULATORS 5V / 200mA AND 5V/200mA SEPARATE VOLTAGE REGULATOR FOR CAN-TRANSCEIVER SUPPLY WITH LOW POWER SLEEP MODE EFFICIENT UC SUPERVISION AND RESET LOGIC 24 BIT SERIAL INTERFACE AN UNPOWERED OR INSUFFICIENTLY SUPPLIED NODE DOES NOT DISTURB THE BUS LINES VS VOLTAGE SENSE COMPARATOR SUPPORTS TRANSMISSION WITH GROUNDSHIFT: SINGLE WIRE: 1.5V, DIFFERENTIAL: 3V
SO20
PowerSO20
ORDERING NUMBERS: L4969MD (SO20) L4969 (PowerSO20)
DESCRIPTION The L4969 is an integrated circuit containing 3 independent Voltage Regulators and a standard fault tolerant low speed CAN line interface in multipower BCD3S process. It integrates all main local functions for automotive body electronic applications connected to a CAN bus.
Figure 1. Block Diagram
VS V1 VREG 1
V2
VREG 2
Watchdog and adjustable RC-Oscillator
NRESET
Identifier Filter V3 VREG 3
WAKE RX TX CANH RTH CANL RTL Fault tolerant low speed CAN-transceiver SCLK 24 Bit SPI SIN SOUT Control and Status Memory NINT
August 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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Figure 2. Pin Connection
GND V1 V2 V3 VS CANH RTL CANL RTH GND
GND WAKE NINT NRES
SCLK NRES NINT WAKE GND GND V1 V2 V3 VS
SIN SOUT TX RX
PSO20
SCLK SIN SOUT TXD RXD GND
SO20
GND GND RTH CANL RTL CANH
Table 1. Pin Functions
Pin No. (PSO20) 1, 10, 11, 20 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 Pin No. (SO20) 5,6, 15, 16 7 8 9 10 11 12 13 14 17 18 19 20 1 2 3 4 Pin Name GND V1 V2 V3 VS CANH RTL CANL RTH RXD TXD SOUT SIN SCLK NRES NINT WAKE Power Ground Microcontroller Supply Voltage Peripheral Supply Voltage Internal CAN Supply Power Supply CANH Line Driver Output CANL Termination Source CANL Line Driver Output CANH Termination Source Act. Low CAN Receive Dominant Data Output Act. Low CAN Transmit Dominant Data Input Serial Data Output Serial Data Input Serial Clock Act. Low Reset Output Act. Low Interrupt Request Dual Edge Triggerable Wakeup Input Function
Table 2. Thermal Data
Symbol Rthj-amb Rthj-case Parameter Thermal resistance junction-ambient Thermal resistance junction-case Value 401) 3 Unit C/W C/W
Note: 1. Typical value soldered on a PC board with 8 cm2 copper ground plane (35m thick).
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Table 3. Absolute Maximum Ratings
Symbol VVSDC VVSTR IVOUT1...3 TSTG TJ VOUT1 VOUT2 VOUT3 Vinli VinliW Vcanh Vcanl Parameter DC operating supply voltage Transient operating supply voltage (T < 400ms) Output currents Storage temperature Operating junction temperature Externally forced output voltage OUT1 Externally forced output voltage OUT2 Externally forced output voltage OUT3 Input voltage Logic inputs: SIN, SCLK, NRES Input voltage WAKE Voltage CANH line
3
Value -0.3 ... +28 -0.3 ... +40 Internally limited -65 ... +150 -40 ... +150 -0.3 ... VS+0.3, max +6.3 -0.3 ... VS+0.3 -0.3 ... VS+0.3, max +6.3 -0.3 ... +7 -0.3 ... VS+0.3 -28 ... +40 -28 ... +40
Unit VVSDC VVSTR IVOUT1...3 TSTG TJ VOUT1 VOUT2 VOUT3 Vinli VinliW Vcanh Vcanl
Voltage CANL line 3
Notes: 1. All pins of the IC are protected against ESD. The verification is performed according to MIL 883C, human body model with R = 1.5kW, C = 100pF and discharge voltage 2000V, corresponding to a maximum discharge energy of 0.2mJ.. 2. Voltage forced means voltage limited to the specified values while the current is not limited. 3. ESD Pulses on CAN-Pins up to 4KV HBM vs GND with all other Pins grounded.
Table 4. Electrical Characteristics VS = 14V, Tj = -40C to 150C unless otherwise specified.
Symbol Supply Current ISSL ISSLWK ISSB All Regulators off (CANH Standby V1 off, V2 off, V3 on (CAN RX only) V1 only (CAN Standby) Timer off (Sleep #1) Timer on (Sleep #2) RXonly Timer off (Standby #1) Timer on (Standby #2) Default (Standby #3) IS All Regulators on, (CAN active, TX high) Additional Oscillator- and Chargepumpcurrent at low VS IOUT1 = -100mA IOUT2 = -10mA No CAN load. VS = 6V; Timer Off VS = 6V; Timer On 6V < VS < 28V IO >-100mA SO20 Package 6V < VS < 28V IO >-150mA PSO20 Package VDP1 Dropout voltage 1@ VS=4.8V IOUT1 = -10mA IOUT1 = -100mA SO20 Package IOUT1 = -150mA PSO20 Package 55 10 4.9 30 70 40 90 4 150 200 440 120 60 135 6 250 300 600 150 A A mA A A A mA Parameter Test Conditions Min. Typ. Max. Unit
ISCP
80 30 5
100 50 5.1
A A V
Voltage Regulator 1 V01 V1 output voltage
4.9
5
5.1
V
0.0 0.0 0.0
0.025 0.25 0.4
0.06 0.6 0.9
V V V
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Table 4. Electrical Characteristics (continued) VS = 14V, Tj = -40C to 150C unless otherwise specified.
Symbol VOL01 Parameter Load regulation 1 Test Conditions IO =-1mA to-100mA SO20 Package IO =-1mA to -150mA PSO20 Package ILIM1 Current limit 1 0.8V < VO1 < 4.5V, VS=6V, SO20 Package 0.8V < VO1 < 4.5V VS=14V, PSO20 Package VOLI1 TOVT1 TOTKL1 Vres Line regulation 1 Overtemp flag 1 Thermal shutdown 1 6V < VS < 28V IO1 = -1mA 6V < VS < 28V 6V < VS < 28V RTC0 = 1 Voltage Regulator 2 and 3 VO Output voltage 6V < VS < 28V IO >-100mA SO20 Package 6V < VS < 28V IO >-150mA PSO20 Package VDP Dropout voltage VS = 4.8V IO UT = 100mA SO20 Package IO UT = 150mA PSO20 Package VOLO Load regulation IO =-1mA to -100mA SO20 Package IO =-1mA to -150mA PSO20 Package ILIM Current limit 0.8V < VO1 < 4.5V, VS=6V, SO20 Package 0.8V < VO1 < 4.5V PSO20 Package VOLI TOVT TOTKL Vtrc tOSC tWDC tRDnom tWDstart Line regulation Overtemp flag Thermal shutdown V2 tracking offset OnChip RC-Timebase Watchdog timebase (2.5ms) Reset pulse duration (1ms) Reset pulse pause (320ms) (startup watchdog) 6V < VS < 28V IOUT = -5mA 6V < VS < 28V 6V < VS < 28V 6V < VS < 28V, IO2 = 0 RC-Adjustment = 0 4.8 5 5.2 V Min. 0 0 -180 -180 Typ. 10 10 -400 -400 Max. 40 40 -800 -800 Unit mV mV mA mA
0 130 175 4.15 3.7
5 140 185 4.5 4.0
30 150 205 4.7 4.2
mV C C V V
Min V1 reset threshold voltage RTC0 = 0
4.8
5
5.2
V
0.0
0.25
0.6
V
0.0 0 0 -180 -180 0 130 150 -90 0.95
0.4 10 10 -400 -400 5 140 165 0 1.1 2498 1024 128
0.9 40 40 -800 -800 30 150 180 +90 1.35
V mV mV mA mA mV C C mV us tOSC tOSC tWDC
Reset and Watchdog
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Table 4. Electrical Characteristics (continued) VS = 14V, Tj = -40C to 150C unless otherwise specified.
Symbol tWDswS Parameter Watchdog window start (Software window Watchdog) Test Conditions SWT = 0 (2.5ms) SWT = 1 (5ms) SWT = 2 (10ms) SWT = 3 (20ms) tWDswE Watchdog window end (Software window watchdog) SWT = 0 (5ms) SWT = 1 (10ms) SWT = 2 (20ms) SWT = 3 (40ms) tWD1C System Watchdog 1 WDT = 0 (80ms) WDT = 1 (160ms) WDT = 2 (320ms) WDT = 3 (640ms) WDT = 4 (800ms) tWD2C System Watchdog 2 WDT = 8 (1s) WDT = 9 (2s) WDT = 10 (4s) WDT = 11 (8s) WDT = 12 (45min) VRESL RPURES Reset output LOW voltage Internal Reset Pull-Up Resistance Propagation delay (rec to dom state) Propagation delay (dom to rez state) Bus output slew rate (r -> d) Cload = 3.3n Cload = 3.3n, RTERM =100 10% ... 90% CLoad = 3.3n IRES = 500u, V1 = 2.5V IRES = 500u, V1 = 1.5V 0 0 80 Min. Typ. 1 2 4 8 2 4 8 16 32 64 128 256 320 400 784 1600 3200 1081344 0.3 0.85 120 0.4 1.4 280 Max. Unit tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC V V K
CAN Line Interface tdrd tddr SRD 0.4 0.4 4 0.5 1.0 1.0 5 1.5 2.0 8 16
s s
V/s K
RRTH, RRTL external Termination resistance (application limit) VCCFS VHRXD VLRXD Vd_r Force Standby mode (fail safe) High level output voltage on RXD Low level output voltage on RXD Differential receiver dom to rec threshold VCANH - VCANL Differential receiver rez to dom threshold VCANH - VCANL No bus failures min VS to turn off CAN-IF and V3
2.20 V1 - 0.9 0 -3.85
4.0 V1 0.9 -2.50
V V V V
Vr_d
No bus failures
-3.50
-2.20
V
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Table 4. Electrical Characteristics (continued) VS = 14V, Tj = -40C to 150C unless otherwise specified.
Symbol VCANHr VCANHd VCANLr VCANLd ICANH ICANL ILCANH ILCANL Parameter CANH recessive output voltage CANH dominant output voltage CANL recessive output voltage CANL dominant output voltage CANH dominant output current CANL dominant output current CANH Sleep mode leakage current CANL Sleep mode leakage current CANH wakeup voltage CANL wakeup voltage CANH single ended receiver threshold CANL single ended receiver threshold CANH overvoltage detection threshold CANL overvoltage detection threshold internal RTH to GND termination resistance Normal mode, No failures. internal RTH to GND termination current Normal mode, Failure EIII internal RTL to VCC termination resistance Normal mode, no failures. internal RTL to VCC termination current Normal mode. (failure EIV, EVI, EVII) internal RTL to VS termination resistance No failures. Low level input voltage High level input voltage Low level input voltage Test Conditions TXD = V1 RRTH < 4K TXD = 0 ICANH = 40mA TXD = V1 RRTL < 4K TXD = 0 ICANL = -40mA TXD = 0 VCANH = 0V TXD = 0 VCANL = 14V Sleep mode. Tj=150C VCANH = 0V Sleep mode. Tj=150C VCANL = 0V VS = 12V Sleep/ standby mode Sleep/ standby mode Normal mode. -5V < CANL < VS Normal mode. -5V < CANH< VS Normal mode. -5V < CANL < VS Normal mode. -5V < CANH < VS VRTH = 1V 1.2 2.4 1.5 2.7 6.5 6.5 30 70 -70 100 -100 0 0 V3 1.4V V3 0.2V 1.4 160 -160 Min. Typ. Max. 0.35 Unit V V V V mA mA
A A
VWakeH VWakeL Vcanhs Vcanls VOVH VOVL RTRTH
1.9 3.1 1.82 3.1 7.2 7.2 45
2.7 3.8 2.15 3.4 8.0 8.0 80
V V V V V V W
ITRTHF
VRTH =V3 - 1V
55
75
100
A
RTRTL
VRT L =V3 - 1V
30
45
85
W
ITRTLF
VRTL =V3 - 1V
-6
-40
-70
A
RTRTLS
Standby/sleep mode. VRTL =1V, 4V
8
13.0
26
K
Digital I/O VSINL VSINH VSCLKL 0 V1 - 0.9 0 0.9 V1 0.9 V V V
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Table 4. Electrical Characteristics (continued) VS = 14V, Tj = -40C to 150C unless otherwise specified.
Symbol VSCLKH VTXL VTXH VWakeL VWakeH VSoutH VSoutL VRXDH VRXDL IohRXD IolRXD IohSOUT IolSOUT IohINT IolINT IohReset IolReset IohWake IolWake tStart Parameter High level input voltage Low level input voltage High level input voltage Low level input voltage High level input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage High level output current Low level output current High level output current Low level output current High level output current Low level output current High level output current Low level output current High level output current Low level output current SIN low to SCLK low setup time (frame start) SIN to SCLK setup time (write) SIN to SCLK hold time (write) SCLK to SOUT delay time (read) SCLK maximum cycle time (timeout) Interframe Gap SCLK frequency range Sense comparator detection threshold CANH groundshift detection threshold Nr of dom to rec edges on CANL to detect permanent rez CANH Nr of dom to rec edges to detect recovery of CANH Operating mode (EI_V) 1 5 0.25 6.0 -1.5 0.5 7.2 -1 1 8.0 -0.6 1.5 RXD = 0 RXD = 5V SOUT = 0 SOUT = 5V INT = 0 INT = 5V RESET = 0 RESET = 5V VWake = 5V VWake = 0V Test Conditions Min. V1 - 0.9 0 V1 - 0.9 0 4.1 V1 - 0.9 0 V1 - 0.9 0 -1.2 1.1 -9.0 18.0 -10.0 18,0 -6,0 5.0 0 -2.2 100 -1.8 1.6 -14.0 24,0 -15.0 24,0 -15,0 6.5 0 -3.4 Typ. Max. V1 0.9 V1 0.9 5.0 V1 0.9 V1 0.9 -2.5 2.2 -18.0 30.0 -20.0 30,0 -25.0 8.0 0.5 -4.5 Unit V V V V V V V V V mA mA mA mA mA mA
A
mA
A A
ns
Serial Data Interface
tSetup tHold tD tCKmax tGAP fSCLK VSmin GSCANH
100 100 500 3.0
ns ns ns ms s MHz V V
Diagnostic Functions
CAN Error Detection NEdgeH 3 Edges
NEdgeHR
Operating mode (EI_V)
3
Edges
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Table 4. Electrical Characteristics (continued) VS = 14V, Tj = -40C to 150C unless otherwise specified.
Symbol NEdgeL Parameter Nr of dom to rec edges on CANH to detect permanent rez CANL Nr of dom to rec edges to detect recovery of CANL CANH to VS short circuit detection time CANH to VS short circuit recovery time CANL to GND short circuit detection time CANL to GND short circuit recovery time CANL to VS short circuit detection time CANL to VS short circuit recovery time CANL to CANH short circuit detection time CANL to CANH short circuit recovery time CANH to VDD short circuit detection time CANH to VDD short circuit recovery time TX permanent dominant detection time (Fail safe) TX permanent dominant recovery time (Fail safe) Minimum dominant time for wake-up via CANH or CANL Minimum pulse time for wakeup via WAKE Test Conditions Operating mode (EII_IX) Min. Typ. 3 Max. Unit Edges
NEdgeLR
Operating mode (EII_IX)
3
Edges
tEIII
Operating mode (EIII) Sleep/ standby mode (EIII) Operating mode (EIII) Sleep/ standby mode (EIII) Operating mode (EIV) Sleep/ standby mode (EIV) Operating mode (EIV) Sleep/ standby mode (EIV) Operating mode (EVI) Operating mode (EVI) Operating mode (EVII) Operating mode (EVII) Operating mode (EVIII) Sleep/ standby mode (EVIII) Operating mode (EVIII) Sleep/ standby mode (EVIII) Operating mode (EX) Operating mode (EX)
1.6 1.6 0.4 0.4 0.4 0.4 10 0.4 0.4 200 0.4 10 1.6 1.6 0.4 0.4 0.4 1
2 2 0.9 0.9 0.9 0.9 30 0.9 0.9 500 0.9 30 1.8 1.8 0.9 0.9 0.9 4
3.6 3.6 1.6 1.6 1.6 1.6 50 1.6 1.6 750 1.6 50 3.6 3.6 1.6 1.6 1.6 8
ms ms
tEIIIR
ms ms
ms ms
tEIV
tEIVR
s ms ms s
ms
tEVI tEVIR tEVII tEVIIR tEVIII
s
ms ms ms
tEVIIIR
ms
ms
tFailTX tFailTXR Wakeup twuCAN twuWK
s
sleep/standby sleep/standby
8 8
22 22
38 38
s s
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1 FUNCTIONAL DESCRIPTION
1.1 General Features The L4969 is a monolithic integrated circuit which provides all main functions for an automotive body CAN network. It features two independent regulated voltage supplies V1 and V2, an interrupt and reset logic with internal clock generator, Serial Interface and a low speed CAN-bus transceiver which is supplied by a separate third voltage regulator (V3). The device guarantees a clearly defined behavior in case of failure, to avoid permanent CAN bus errors. The device operates in four basic modes, with additional programming for V1 Standbymodes in CTCR:
Mode Sleep #1 Sleep #2 V1 V2 V3 Timer/WDC Off On (250KHz) Off On (250KHz) On (1MHz) On (1MHz) On (1MHz) CAN-IF Standby Standby Standby Standby Standby RX-Only Normal Ityp 40u 80u 170u 210u 440u 4mA 5mA LP1, LP0 (CTCR) x,x x,x 1,1 1,0 0,0 x,x x,x Remarks No Timer based wakeup Timer active No Watchdog or Timer Watchdog or timer active Watchdog or timer activ, POR default Active during Busactivity to filter ID, automatic fall back to Sleep when Bus idle No Currents from CAN or Regulators
Off Off Off Off Off Off
Standby #1(*1) On Off Off Standby #2(*1) On Off Off Standby #3 RXOnly Normal On Off Off Off Off On On On On
(*1) Note, that in order to enter either Standby #1 or Standby #2 the Startup-Watchdog has to be acknowledged (see Chapter 1.2), in Standby #1, the Window Watchdog has to be disabled as described in Chapter 2.5, to allow the decativation of the internal oscillator.
1.1.1 V1 Output Voltage The V1 regulator uses a DMOS transistor as an output stage. With this structure very low dropout voltage is obtained. The dropout operation of the standby regulator is maintained down to 4V input supply voltage. The output voltage is regulated up to the transient input supply voltage of 40V. With this feature no functional interruption due to overvoltage pulses is generated. The output 1 regulator is switched off in sleep mode. 1.1.2 V2 Output Voltage The V2 regulator uses the same output structure as the output 1 regulator except to being short circuit proof to VS, and to be rated for the output current of 200mA. The V2 output can be switched on and off through a dedicated enable bit in the control register. In addition a tracking option can be enabled to allow V2 follow V1 with constant offset. This feature allows consistent A/D conversion inside the C (supplied by V1) when the converted signals are referenced to V2. The maximum voltage that can be applied to V2 is VS + 0.3V up to a max VS of 40V. 1.1.3 V3 Output Voltage The third voltage regulator of the device generates the supply voltage for the internal logic and the CAN-transceiver. In operating mode it is capable of supplying up to 200mA in order to guarantee the required short circuit current for the CAN_H driver. The sleep and operating modes are switched through a dedicated enable bit. 1.1.4 Internal Supply Voltage A low power sleep mode regulator supplies the internal logic in sleep mode.
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1.2 Power-Up, Initialization and Sleep mode transitions The following state-diagram illustrates the possible mode transitions inside the device. As a prerequisite, a SPI-connection to the uC with the correct CRC-algorythms is required. During the debug phase the NRES line can be forced high externally (connect to V1) to deactivate the startup failure mechanis keeping V1 will alive. Figure 3.
After POR, V1 up or externally forced reset through low NRES, the STARTUP STATE is entered The forced sleep mode is left upon wakeup through either CAN or edge on WAKE. Applying a permanent wakeup (i.e. both CAN-lines dominant) prevents V1 from being turned off (can be used during System debugging)
V1 Low NRES Low WAKEUP STARTUP V1 active V2, V3, CAN off WDC-ACK
WAKEUP
Forcing NRES high externally, fail will not be incremented (Emulation)
t=320ms t=1ms
STARTUP FAILURE RESET low (fail ++)
fail = 7
FORCED SLEEP V1 off No Reset
A missing ACK within 320ms will initiate a STARTUP FAILURE phase (RESET low).
WDC-FAIL
Dependig on the value from the last WDC-ACK, another one has to be written within the specified time frame (SWDC[1:0]). A failure will activate the STARTUP STATE
WDC-ACK & WDEN SET
If no WDC-ACK is received within seven retrials the voltage regulator V1 will be turned off by entering the FORCED SLEEP state.
Writing to the WDCregister (WDC-ACK) the NORMAL STATE is entered.
The Window supervision can temporarily be deactivated for the time programmed during the last WDC-ACK (WDT[3:0]). Upon rewriting (WDC-ACK) or expiry of the timer, the NORMAL STATE is reentered.
NORMAL MODE WDC-ACK WINDOW WDC t=tWIN2 WDC-OK ACTIVE
WINDOW WATCHDOG REFRESH
WDEN SET
TIMER ACTIVE (restart by double WDC-ACK & WDEN)
WND SET DISAR SET
TIMEOUT | WDC-ACK
If during the last WDC-ACK WND has been set (after releasing write lock, see description of Watchdog Control Register) the Window watchdog is deactivated, and no uC supervision is active. Here the timer can be used to generate time events (i.e. wakeup uC from stop)
NORMAL MODE WINDOW WDC DISABLED WAKEUP DISAR SET
WDEN SET TIMEOUT | WDC-ACK
TIMER ACTIVE (restart by double WDC-ACK & WDEN)
WAKEUP &V1_UV
Programmed SLEEP V1 OFF No Reset
Setting DISAR (see Voltage Regulator Control Register) Voltage regulator V1 is turned off, and the output voltage is decreasing depending on the external load and blocking capacitor. Note, that during this transition no Reset will be generated (due to Debugmode). Upon wakeup howewer NRES will be pulled low, if V1was below the programmable reset threshold (V1_UV).
WAKEUP&V1_UV
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1.3 CAN Transceiver
- Supports double wire unshielded busses - Baud rate up to 125KBaud - Short circuit protection (battery, ground, wires shorted) - Single wire operation possible (automatic switching to single wire upon bus failures) - Bus not loaded in case of unpowered transceiver The CAN transceiver stage is able to transfer serial data on two independent communication wires either deferentially (normal operation) or in case of a single wire fault on the remaining line. The physical bitcoding is done using dominant (transmitter active) and overwritable recessive states. Too long dominant phases are detected internally and further transmission is automatically disabled (malfunction of protocol unit does not affect communication on the bus, "fail-safe" - mechanism). For low current consumption during bus inactivity a sleep mode is available. The operating mode can be entered from the sleep mode either by local wake up (C) or upon detection of a dominant bit on the CAN-bus (external wake up). Ten different errors on the physical buslines can be distinguished: 1.3.1 Detectable Physical Busline Failures
N Type of Errors Conditions
Errors caused by damage of the datalines or isolation I II III IV V VI VII CANH wire interrupted (tied to Ground or termination) CANL wire interrupted (floating or tied termination) CANH short circuit to VBAT (overvoltage condition) CANL short circuit to GND (permanently dominant) CANH short circuit to GND (permanently recessive) CANL short circuit to VBAT (overvoltage condition) CANL shorted to CANH Edgecount difference > 3 Edgecount difference > 3 V(CANH) > 7.2V after 32us V(CANL) < 3.1V & V(CANH)-V(CANL) < -3.25V after 1.3ms Edgecount difference > 3 V(CANL) > 7.2V after 32us V(CANH) - V(CANL) < -3.25V after 1.3ms
Errors caused by misbehavior of transceiver stage VIII IX CANH short circuit to VDD (permanently dominant) CANL short circuit to VDD (permanently recessive) V(CANH) > 1.8V & V(CANH) V(CANL) < -3.25V after 2.5ms Edgecount difference > 3
Errors caused by defective protocol unit X CANH, CANL driven dominant for more than 1.3ms
Not all of the 10 different errors lead to a breakdown of the whole communication. So the errors can be categorized into 'negligible', 'problematic' and 'severe':
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1.3.2 Negligible Errors 1.3.2.1 Transmitter Error I and II (CANH or CANL interrupted but still tied to termination) Error IV and VIII (CANH or CANL permanently dominant by short circuit) In all cases above data can still be transmitted in differential mode. 1.3.2.2 Receiver Error I and II (CANH or CANL interrupted but still tied to termination) Error V and IX (CANH or CANL permanently recessive by short circuit) In all cases above data can still be received in differential mode. 1.3.3 Problematic Errors
1.3.3.1 Transmitter Error III and VI (CANH or CANL show overvoltage condition by short circuit) Data is transmitted using the remaining dataline (single wire) 1.3.3.2 Receiver Error III and VI (CANH or CANL show overvoltage condition by short circuit) Data is received using the remaining dataline (single wire) 1.3.4 Severe Errors 1.3.4.1 Transmitter Error V and IX (CANH or CANL permanently recessive by short circuit) Data is transmitted on the remaining dataline after short circuit detection Error VII (CANH is shorted to CANL) Data is transmitted on CANH or CANL after overcurrent was detected Error X (attempt to transmit more than 10 successive dominant bits (at lowest bitrate specified) Transmission is terminated (fail safe) 1.3.4.2 Receiver Error VII (CANH is shorted to CANL) Data is received on CANH or CANL after detection of permanent dominant state Error IV and VIII (CANH or CANL permanently dominant by short circuit) Data is received on CANH or CANL after short circuit was detected Error X (reception of a sequence of dominant bits, violating the protocol rules) Data is received normally, error is detected by protocol-unit The error conditions is signaled issuing an error flag inside a dedicated register which is readable by the C through the serial interface. The information of the error type (I through X) is also stored into this register.
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1.4 Oscillator A low power oscillator provides an internal clock. In sleep mode (Watchdog active) the output frequency is 250kHz, if the Watchdog function is not requested, the internal Oscillator is switched off. In standby and operating mode the oscillator is running at 1MHz, and can be calibrated in a range from -16% to +16% using the C-XTAL as a reference. 1.5 WatchdL4969og A triple function programmable watchdog is integrated to perform the following tasks: - Wakeup Watchdog: When in sleep or standby mode the watchdog can generate a wakeup condition after a programmable period of time ranging from 80ms up to 45 minutes - Startup Watchdog: Upon V1 power-up or C failure during SPI supervision (see SW-Watchdog) a reset pulse is generated periodically every 320ms for 2.5ms until activity of the C is detected (SPI sequence) or no acknowledge is received within 7 cycles (2.2sec). In this condition the device is forced into Sleep mode until a Wakeup is detected and a startup cycle is reinitialized. - Window Watchdog: After passing the startup sequence, this watchdog request an acknowledge by the C via the SPI within a programmable timing frame, ranging from 2.5 ... 5ms up to 20 ... 40ms. Upon a missing or misplaced acknowledge the Startup Watchdog is initialized. 1.6 Reset
1.6.1 Power-on Reset Upon Power-on (VS > 3.5V), the internal reset forces the device into a predefined power-on state (see 1.1): Standby #3:V1 on V2 off V3 off,CAN-Standby mode, ID-Filter disabled, Startup Watchdog active With VS below 5V the regulator V1 will follow VS with minimum drop. The C retrieves a reset if V1 is dropping below a programmable voltage level of either 4.5V (default) or 4.0V. The programmed state of the L4969 remains unchanged. The act. low Resetpulse duration is fixed internally by an open-drain output stage to 1ms. However, this time can be externally extended by an additional capacitance connect between NRESET and GROUND which is then charged by the internal pull-up of typ. 120K. Depending on the Reset-Input-Threshold of the uC (UTR), the reqired Capacitance for a typical tD can be calculated as follows: CEXT = -tD / (120E3 ln(1-UTR/V1))). To obtain a reset-pulse duration of tD = 50ms with UTR/V1 = 0.5, a Capacitance of CEXT= -50E-3 / (120E3 ln 0.5) = 600nF is required. Figure 4. V1 120K NRES
to Reset Input of uC
CEXT
1.6.2 Undervoltage Reset Upon detection of a V1 voltage level below a programmable voltage level of either 4.5V (default) or 4.0V,the NRES-pin is pulled low. Since this undervoltage detection is additionally sampled periodically every ms, the NRES low time will be extended by up to 1 ms if V1 was low (V1 UV) at the sampling point (see below).
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L4969
Figure 5. 1ms sampling V1UV NRES 1.6.3 Reset signalling during Sleepmode When entering the sleep mode by writing 1 to DISAR in the VRCR register, the Voltageregulators and their references will be deactivated to allow minimum current consumption. By removing the V1 reference, the outputvoltage is no longer supervised and thus NO reset will be generated. Now two scenarios are possible (see statediagram in chapter 1.2): 1) Wakeup with V1 still above reset threshold: V1 will be reactivated and Normal mode is resumed 2) Wakeup with V1 below reset threshold: V1 will be activated, NRES will go low and remain low until V1 is above reset threshold and Startup mode is entered. The scenario 2 is the most critical when used with uC that do not have their own POR circuitry. In this case V1 will ramp down with an unknown application state. To guarantee a proper shut off of an uC without an internal POR circuitry the following mechanism can be utilized: The L4969 uses a bidirectional Reset to detect a possible Watchdog failure of the uC. If this failure condition is detected, NRES will be forced low for 1 ms (with activated timer) or until a wakeup condition occurs (WDEN bit in WDC register reset, thus RC-oscillator will be switched off during sleep). Two methods can be used to allow a proper sleep transition: - With Timer (WDEN=1): immediately after setting DISAR the uC has to program its WDC to generate a failure causing the L4969 to detect a low level on NRES followed by an automatic 1ms pulse extension. If V1 is ramping down slow, Cext has to be defined in a way, that NRES will stay below the input threshold of the uC until V1 is in a safe level. - Without timer (WDEN=0): same procedure as above, but uC has to generate a Reset within 1 ms after WDEN has been cleared. NRES will then stay low, until a wakeup condition occurs. Figure 6. .
DISAR
REF REG R1
V1
R2
NRES
WDC
1ms RC-Osc
CEXT
uC
L4969
1.7 Identifier Filter A 12-Bit CAN-ID-filter is implemented allowing wakeup via specific CAN-messages thus aiding the implementation of low power partial communication networks like standby diagnostics without the need to power-up the whole network. To guarantee the detection of the programmed Identifiers, the local RC-oscillator can be calibrated to allow the programmable Bittime logic to extract the incoming stream with a maximum of tolerance over temperature deviation. 1.8 Ground Shift Detection
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L4969
In case of single wire communication via CANH the signal to noise ratio is low. Detecting the local ground shift can be used as an additional indicator on the current signal quality. The information of the integrated ground shift detector will be refreshed upon every falling edge on TX and can be read from the CAN Transceiver Status Register (CTSR). It will be set, if V(CANH) < -1V, reset if V(CANH > -1V) at the falling edge of TX. 1.9 Thermal Protection The device features three independent thermal warning circuits which monitor the temperature of the V1 output, the V2 output and the CAN_H and CAN_L drivers together with voltage regulator V3. Each circuit sets a separate overtemperature flag in a register which is read and writable by the serial interface. The overtemperature flags cause an interrupt to the C. The C is able to switch V1, V2 and CAN drivers on and off through dedicated enable registers. To enhance system security following strategy is chosen for thermal warning and shutdown: - 3 independent warning flags are set at 140C for V1, V2 and V3 /CAN-Transceiver - at 170C V2 and V3 switched off - at 200C V1 is switched off - V2 and V3 can be switched on again through the C - V1 can be switched on again at wake-up (Watchdog wake-up, CAN wake-up, external wake-up) Note, that if no wakeup source is set for V1 a 1sec watchdog timeout will be established to enable a proper retry cycle. 1.10 Serial Interface (SPI) A standard serial peripheral interface (SPI) is implemented to allow access to the internal registers of the L4969. A total of 12 Registers with different datalengths can be directly read from or written to, providing the requested address at the beginning of a dataframe. Upon every access to this interface, the content of the register currently accessed is shifted out via SOUT. All operations are performed on the rising edge of SCLK. If a frame is not completed, the interface is automatically reset after 1.5ms of SCLK idle time (auto timeout detection). If a message is corrupted (additional or missing SCLK pulses), the application software can detect this by evaluating the returned value of the crc and force a communication gap of min 1.5ms to allow communicvation recovery. A corruption can be caused during startup of the uC and SPI initialization. The application should then wait at least 1.5ms after SPI init prior to starting the communication. The dataframe format used described on the next page:
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L4969
1.10.1General Dataframe Format: Figure 7.
SIN 7
ADR/CMD 0 15
Datafield 1 (W/R) 8
Datafield 2/CRC (W/R) 23 15
SOUT 7
ADR/CMD 0 15
Datafield 1 (R) 8
Datafield 2/CRC (R) 23 15
SCLK
99AT0015
Data is sampled on the rising edge of the clock and SOUT will change upon SCLK falling. SOUT will show a copy of SIN for the Address/Command field for initial data path checks. Independent of the command state, SOUT will show the content of the register addressed. SIN contains either data to be written or arbitrary data for all other operations. The transaction will be terminated with four bit of data followed by a 4-Bit wide CRC (Cyclic Redundancy Check) as a result of either SIN related data or calculated automatically on data returned via SOUT. Here the C has to provide the correct sequence in order to get the write command activated inside. A CRC-failure is signalled via NINT. For returned data the CRC can also be used to verify a successful transfer. 1.10.2 Address/Command Field Figure 8.
7 0 1 ADR3 ADR2 ADR1 ADR0 C1
0 C0
Frame start sequence always has to be transmitted as 0 1
Addressfield specifying the Control/Status word to be accessed
SPI command: 00: Read register 01: Clear IFR 10: illegal command 11: Write register
The Address/Command field starts with a 2-Bit start sequence consisting of `01'. Any other sequence will lead to a protocol error signalled via the NINT. The addressfield is specifying the register to be accessed. The SPI command flags allow in addition to the normal read/write operation to clear the Interrupt flag register after read.
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L4969
1.10.3 Datafield #1 Figure 9.
D7
D6
D5
D4
D3
D2
D1
D0
Lower 8 Bit of 12 Bit data SIN: Data to write SOUT: Data currently in selected register
99AT0017
Datafield #1 contains either the lower 8 bits of a 12-Bit frame or the complete byte of an 8-Bit transfer. Note, that SOUT is always showing the content of the register currently accessed and not a copy of SIN as during the Address/ Command field. 1.10.4 Datafield #2 /CRC Figure 10.
D11
D10
D9
D8
CRC3
CRC2
CRC1
CRC0
Upper 4 Bit of 12 Bit data (Zero if 8 Bit data)
SIN: Data to write SOUT: Data currently in selected register
99AT0018
CRC Check sequence to be appended to tranferred data Note that upon CRC check failure no write operation will be performed SIN: CRC of SIN sequence SOUT: CRC of SOUT sequence
Datafield #2 contains either the upper four bits of a 12-Bit frame or zeros in case of an 8-Bit transfer. This field is followed by a four bit CRC sequence that is calculated based upon the polynom 0x11h (17 decimal). This sequence is simply the remainder of a polynomial division performed on the data previously transferred. If the CRC appended to the SIN sequence fails, any writing will be disabled and an error is signalled via NINT. Another remainder is calculated on the SOUT stream and appended accordingly to allow the application software to validate the correctness of incoming data. To aid evaluation, the CRC checking can be turned off by writing arbitrary data with a valid CRC to address 15. CRC-checking will be reenabled upon another operation of this kind (Toggled information).
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1.11 Memory Map Table 5.
ADR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
L4969 Memory Map
MSB D10 D9 D8 D7 EUV3 ACT Undefined Register Memory RES CG1 WDEN ISET ESPI RES A11 D11 PS23 ISET RES A10 D10 PS22 IRES RES A01 D01 PS21 UV23 GSH A00 D00 PS20 UVVS EX B11 E11 PS13 D6 EUV2 TXEN RES CG0 WND IRES OVT3 EVIII B10 E10 PS12 D5 RTC0 RES RES PGEN SWT1 EUV OVT2 EVII B01 E01 PS11 D4 TRC RES RES SIGN SWT0 EOVT OVT1 EVI B00 E00 PS10 D3 RES RES TM1 ADJ3 EEW WKE EIV C11 F11 TD3 D2 ENV3 LP2 TM0 ADJ2 ECW WKC EIII C10 F10 TD2 D1 ENV2 LP1 TMUX ADJ1 WDT1 EWW WKW EII C01 F01 TD1 D0 DISAR LP0 TEN ADJ0 WDT0 EIFW WKIF EI C00 F00 TD0
Group VRCR CTCR GPTR RCADJ WDC GIEN IFR CTSR ID01 ID23 BTL NAV NAV NAV TEST SYS
WDT3 WDT2
Undefined Register Memory T11 T10 T09 T08 T07 NCRC T06 STAT T05 WNDF T04 STF T03 OTF T02 UCF T01 WAKE T00 NPOR
Undefined Register Memory
The memory space is divided up into 16 different registers each being directly accessible using the SPI. Each register contains specific information of a functional group. In general al reserved bitpositions (`RES') have to be written with `0'. Undefined bits are read as `0' and cannot be overwritten. In addition there is one register (CTSR) being read only, thus any write attempt will leave the register content unchanged. Certain interlock mechanism exist to prevent unwanted overwriting of important functions i.e. voltage regulators or oscillator adjustments. These mechanisms are described with the functions of these registers.
*1) "shorted to ..."
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2 CONTROL AND STATUS REGISTERS The functionality of the device can be observed and controlled through a set of registers which are read and writable by the serial interface. 2.1 ADR 0: VRCR Voltage Regulator Control Register
Figure 11. D7 EUV3 EUV2 RTC0 TRC RES ENV3 ENV2 D0 DISAR
Enable undervoltage detection on Regulator #2 and #3 (see note below) Set reset threshold value to 4.0V Default value is `0' (4.5V)
Has to be written as `0'.
Disable all Regulators (Go to Sleep) Note, that at least one Wakeup Source without a pending wakeup is required to enable access. This bit will be automatically set upon the system failures Overtemperature V1 or watchdog startup failure. Note, that no reset will be generated from low V1 during Sleep mode transition The Reset line has to be forced low externally, or through a window failure DISAR will be cleared upon a valid wakeup signal which is either defined in GIEN or is forced to WAKE or CAN after a system failure Enable Regulator #2. Default value is `0' (disabled) This bit will be automatically reset upon Overtemperature at Regulator #2.
Enable Regulator #2 tracking option to have V2 following V1 with constant offset Default value is `0' (disabled) Enable Regulator #3 . V3 will be activated by either setting ENV3 or upon enabling of the CAN Lineinterface Default value is `0' (disabled) This bit will be automatically reset upon Overtemperature from CANIF or Regulator #3
DISAR V1
Note, that due to the large initial charging current of the output capacitors, the activation of V2 AND V3 within the same command is not recommended also leaving ENV2 or ENV3 set when setting DISAR can therefor not be recommended (after wakeup V1 AND V2 or V3 would be turned on) TRC DISAR & ENV2 (DISAR & ENV3 | ACT) & TSDV3 REF V2 V3
V3 will be activated upon VRCR.ENV3 or CCTR.ACT without pending thermal shutdown
Note, that when using the Undervoltage-detection, EUV2 and EUV3 have to be activated AFTER V2 or V3 have been turned on and settled (t > 1ms). Otherwise unwanted undervoltage can be detectected during turn on of the corresponding voltage regulator.
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2.2 ADR 1: CTCR CAN-Transceiver Control Register
Figure 12. D7 ACT TXEN RES RES RES LP2 LP1 D0 LP0
Standby-mode control (V1 only, see 1.1)
CAN-Transceiver application control 0X : Standby / Sleep
enable Auto-Osc-Off reduce Osc-frequency to 250KHz
10 : Receive only mode A (Readback TX, if not EX) 11 : Normal Operation Note, that TXEN is automatically reset upon occurence of EX (TX permanent dominant) and has to be reprogrammed after problem correction to enter normal mode.
Reserved bits (`RES') have to be written as `0'.
Three basic operating modes are available using different logic combinations on ACT and TXEN. Each of these modes in conjunction with other inputs has its unique combination of parameters inside the specification: Table 6. Operating Modes of the CAN Lineinterface
Input Signals ACT 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TXEN X 0 0 0 1 1 1 1 1 X X X X X X X TX X 1/0 1 1 1 0 1 1 0
*1
Output Signals CANL RTL RTL RTL V3 ON ON ON ON RTL RTL RTL ON ON ON ON RTL RTL RTL x3 VDD VS*1 GND*1 CANH*1 ON ON ON ON ON ON ON ON Mode Standby RXonly RXonly RXonly Normal Normal Normal Normal Error X Error VII, VIII Error EIII, VII, VIII Error EI_V Error EII_IX Error EVI Error EVII, EIV Error EVII RTL VBAT VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD ISRC ISRC ISRC RTH GND GND GND GND GND GND GND GND GND ISRC ISRC GND GND GND GND GND CANH OFF OFF OFF OFF ON VDD ON ON OFF OFF OFF ON ON ON ON ON CANL OFF OFF OFF OFF ON GND ON ON OFF ON ON ON ON OFF OFF OFF CANH CANH CANH 1 CANL CANL 1 0 RX 1 TX
CANH RTH RTH RTH RTH RTH RTH RTH VDD*1 VS*1 GND x3 RTH RTH CANL*1
1 1 1 1 1 1 1
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2.3 ADR 2: GPTR Global Parameter and Test Register
Figure 13. D7 RES RES RES RES TM1 TM0 TMUX D0 TEN
This register is to be used for testpurpose only, all bits have to remain `zero' 2.4 ADR 3: RCADJ RC-Oscillator Adjust register
Figure 14.
D7 CG1 CG0 PGEN ADJ4 ADJ3 ADJ2 0: 0% 1: -4% ADJ1 0: 0% 1: -2%
D0 ADJ0 0: 0% 1: -1%
0: 0% 0: 0% 1: +16% 1: -8%
Program enable (read only) Bit will be set after 'Finish cycle measurement', and reset after register write
RC Oscillator Frequency Adjust default value 10000 Note, that programming is only enabled with PGEN set
Test cycle request A low pulse on NINT for a fixed period of time can be requested for XTAL synchronization 99AT0022
00: No request (Adjustment disabled) 01: 2.5ms low cycle on NINT (repetitive) 10: Finish cycle measurement 11: No request (Adjustment disabled)
During normal operation the C can set CG1 and CG0 to `01' to force a 200Hz rectangular waveform on NINT with 50% duty cycle. Note, that all other pending interrupts have to be cleared before. After the XTAL driven timer of the C calculated the relative cycle time and the corresponding deviation, CG1 and CG0 have to be set to `10' to disable the adjustment cycle on NINT. From the deviation calculated by the C, the correction factor of the RC-oscillator -15% to + 16% can be reprogrammed with CG1 and CG0 set to `00' or `11'. (`11' can be used to indicate that calibration has already been performed). Note, that overwriting this register is only valid, if the cycle measurement was started and terminated properly. This can be tested by evaluating PGEN either prior to or during correction (Read back via SOUT). Note also, that any write to the WDC register will reset the timer and thus reset the phase of the testcycle. Therefore a cyclic access to the window watchdog during the pulsewidth measurement has to be avoided and the timer watchdog to be used instead (i.e. 1sec)
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Figure 15. State transition during oscillator calibration
"No Request"
CG=00 CG=01 "2.5ms cycle CG=10 "Finish Cycle" "Update ADJ" on NINT" CG=11 Start time measurement at rising edge Calculate Write offset Offset Watchdog and Interrupt can be enabled
Watchdog and Interrupt has to be disabled 2.5
ADR4: WDC Watchdog Control Register
Figure 16.
D7 WDEN WND SWT1 SWT0 WDT3 WDT2 WDT1 D0 WDT0
Disable Window Watchdog, only allowed with PGEN set, see previous table for Osc adjust
Enable Wakeup Watchdog, Window Watchdog will be automatically deactivated until wakeup watchdog expires
Software Window Watchdog timing configuration 00 : 2.5 - 5ms 01 : 5 - 10ms 10 : 10 - 20ms 11 : 20 - 40ms
Reserved bits (`RES') have to be written as `0'.
Wakeup Watchdog timing configuration 0000 : 80ms 0001 : 160ms 0010 : 320ms 0011 : 640ms 0100 : 800ms 1000 : 1sec 1001 : 2sec 1010 : 4sec 1011 : 8sec 1100 : 45min
The Startup Watchdog is not programmable and will always generate a 1.0ms low cycle on NRESET followed by a 320ms high cycle until an Acknowledgment will occur. If no Acknowldege is received after the 7th cycle, the device will automatically be forced into Sleep mode. Acknowledgment and Reset of Startup and Window Watchdog is automatically performed by overwriting (or rewriting) this register. Note, that with WDEN set, a cyclic setting of IFR.WKW after the programmed Wakeup time will occur. 2.5.1 Watchdog configuration:
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L4969
Figure 17.
POR NRESET forced low externally Wakeup Prog Sleep Ack ExtWake CAN-Wake Startup missing Ack Forced Sleep Wd (after 350ms) missing Ack
Ack
Timeout Window WR Wakeup Wd WR & WDEN Timer
Note: WR, writing to this address, will restart the timer
After power-on-reset of VS and V1 or wakeup from Sleep or NRESET being forced low externally, the Startup Watchdog is active, supervising the proper startup of the V1 supplied uC. Upon missing SPI write operation to the WDC register after 7 reset cycles (1ms active, 320ms high) the Sleep mode is entered. Leaving the forced Sleep mode will be automatically performed upon wakeup via CAN, an edge on WAKE or upon device powerup. After successful startup, the Window Watchdog supervision is activated, meaning, that the uC has to send an acknowledge within a predefined, programmable window. Upon failure, a reset is generated and the Startup Watchdog is reactivated. If the Timer function is requested, the window watchdog is deactivated until expiry of the wakeup time, or rewriting of this register. Note, that any write to this register will reset the timer. 2.5.2 Startup Figure 18.
V1 1ms NRESET Startup Acknowledgement via SPI within 320ms NRESET Startup Acknowledgement via SPI within 640ms NRESET No Startup Acknowledgement via SPI within 2.3s (Device will enter Sleep mode)
After powerup, the L4969 is expecting the uC to send an acknowledgement within a predefined segmented timing frame of 7 x 320ms. A missing acknowledgement until after the 2.3s will force the device into sleep mode until either external or CAN wakeup or POR cause a restart of the sequence above. 2.5.3 Window Watchdog
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L4969
Figure 19.
2,5 .. 20ms 50% Early (late) Acknowlede supervision 5 .. 40ms Early (late) Acknowlede supervision Acknowledge is restarting Window
After successful acknowledgement of the Startup sequence, the Window watchdog is automatically activated and controlling proper uC activity by supervising an incoming acknowledge to ly within a predefined programmable window. Upon every acknowledge the watchdog is restarting the window.
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2.5.4 Wakeup Watchdog Figure 20.
Window Wd Timer (80ms .. 45min) Window Wd
Ack Window & Start Timer NINT
restart timer at any time writing WDC twice
Timeout and resume Window Wd
Interrupt active upon timeout (via GIEN)
If the Timer is activated during Normal mode by setting WDEN in WDC, an "acknowledge-free" sequence is started for a predefied programmable time. Window Watchdog activity is resumed after expiry of the timer. To be able to detect the timeout, the corresponding interrupt enable must be set in GIEN. This mode can also be used to allow a bootstrap loader mode with longer execution times than the maximum specified window. Correct startup of this loader is safely detected upon missing response following the timeout. The timer can always be restarted by rewriting WDEN twice in WDC with a new timing.
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2.6 ADR5: GIEN Global Interrupt Enable Register
Figure 21.
D7 ISET IRES EUV EOVT EEW ECW EWW
D0 EIFW
Enable Interrupt upon CAN error detection Enable CAN wakeup / Interrupt Enable Interrupt upon CAN error recovery Enable Interrupt upon VS / VREG Undervoltage
Enable Identifier based wakeup / Interrupt Enable Wakeup,/ Interrupt via Watchdog
Enable Wakeup / Interrupt via edge on WAKE Enable Interrupt upon Overtemp. Warning
2.7
ADR6: IFR Interrupt Flag Register
Figure 22. D11 ESPI ISET IRES UV23 UVVS OVT3 OVT2 OVT1 WKE WKC WKW D0 WKIF
CAN Linefailure detected (ISET) removed (IRES)
VS < 7.2V detected V2 or V3 Undervoltage
Signal edge on WAKE detected Wakeup condition via CAN detected Watchdog timeout detected Identifier passed CAN ID-Filter
CRC- / Format Error or SCLKTimeout detected by SPI (non maskable)
Overtemperature Warning level reached OVT1 : T(V1) > 140degC OVT2 : T(V2) > 140degC OVT3 : T(V3) > 140degC
Reserved bit (`RES') has to be written as `0'.
Except ESPI all bits in this register are maskable in GIEN. Any masked bit will force NINT low until the register content is reset (either explicitly or by SPI `clear register).
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2.8 ADR7: CTSR CAN Transceiver Status Register
Figure 23. D11 RES RES RES GSH EX EVIII EVII EVI EIV EIII EII_IX D0 EI_V
CANH < -1V at falling edge TX TX permanent dominant detected (TXD = `0', t > 1.3ms) CANH permanent dominant detected (CANH > 1.8V, t > 1.3ms)
CANL short circuit to VS detected (CANL > 7.2V, t > 32us) CANL permanent dominant detected (CANL < 3.1V, t > 1.3ms)
Single wire communication detected (edge count difference > 3) EI_V : CANH off EII_IX : CANL off
Short circuit CANH to CANL detected (CANH - CANL > -3.25V, t > 1.3ms)
CANH short circuit to VS detected (CANH > 7.2V, t > 32us)
Reserved bits (`RES') are always read as `0'
Note, that this register is read only and only provides the unlatched information on current buserrors.
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2.9 ADR 8 and 9: ID01, ID23 Identifier Filter Sequence Select Register
Figure 24.
SEGA ID10 SOF 4/2 Demux 00 ID9
SEGB ID8 ID7
SEGC ID6 ID5
SEGD ID4 ID3
SEGE ID2 ID1
SEGF ID0 RTR
4/2 Demux 00
A00
F00
A01
F01
A10
11
F10
11
A11
F11
99AT0028
PASS
Identifier of CAN Frame can be divided up into 6 segments numbered from `A' to `F'. For each segment a filter register is implemented, enabling different pass functions on every two bit wide block. Segments A through C (ID01) are located at ADR 8 with MSB `C11' Segments D through F (ID23) are located at ADR 9 with MSB `F11' Note, that clearing a complete segment disables the whole filter.
SEGE SEGD SEGF Examples: 10 01 00 Identifiers to pass: 10 01 01 00 01 01 01 01 01 01 11 01 10 00 10
SEGA SEGC SEGB
Valid sequence for each segment SEGA: A10, A00 SEGB: B01 SEGC: C01, C00 SEGD: D10, D01 SEGE: E11, E01, E00 SEGF: F10, F01
ID bits to be set 0101 0010 ID01: 0011 0010 0101 0011 0110 1011 ID01: 0110 1011 0110 0011
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2.10 ADR 10: BTL Identifier Filter Bittimelogic Control Register Figure 25.
D11 PS23 PS22 PS21 PS2 PS13 PS12 PS11 PS10 TD3 TD2 TD1
D0 TD0
Phasesegment 2 length configuration tPSEG2 = 1us * PSEG2
Phasesegment 1 length configuration tPSEG1 = 1us * (1 + PSEG1)
Dominant to Rezessive bitlength difference control
td = tdom - trez
Bittime synchronization mechanism
t = 1u
tPSEG1 Sample Point
99AT0030
tPSEG2
The total bitlength equals the sum of 1 + PSEG1 + PSEG2 in units of s. The location of the sampling point is determined by the length of PSEG1. At the start of frame (initial recessive to dominant edge) the bitlength counter is reset. Upon every signal edge the counter will be lengthened or shortened according to location of the transition within the programmed boundaries of PSEG1 or PSEG2. If the edge lies within PSEG1 additional cycles are inserted in order to shift the sampling point to a safe location after the settling of the input signal. If the signal transition is located within PSEG2, this segment will be shortened accordingly with the goal of the next edge to lie at the beginning of PSEG1. The amount of cycles one segment is lengthened or shortened is determined by the type of edge (rec -> dom or dom -> rec) and the programming of TD: The resynchronization jump width will be either set to `1' (dom -> rec edge) or to 1 + TD (rec -> dom edge). Note, that the length of one timequanta depends on the offset of the on chip RC-oscillator and therefore on the accuracy of calibration (see register RCADJ (ADR 3) for details on frequency correction)
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2.11 ADR 15: SYS System Status Register Figure 26. D7 NCRC STAT WNDF STF OTF UCF WAKE D0 NPOR
CRC-Checking disabled Reserved status flag (test only) Warm start after failure of Window watchdog
Cold Start after low VS Warm start after leaving prog. Sleep mode
Warm start after V1 Overtemp failure
Warm start after < 7 missing Ack during Startup
Warm start after 7 missing Ack during Startup
The lower 6 bit of this register can be used to analyze the reason of startup (after NRESET low). This information is valid until the first Watchdog-Acknowldge, and will then be reinitialized to 000001.
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3 INTERRUPT MANAGEMENT
Figure 27.
D11 ESPI ISET IRES UV23 UVVS
IFR OVT3 OVT2 OVT1 WKE WKC
D0 WKW WKIF
ISET D7
IRES EUV
EOVT
EEW
ECW
EWW EIFW D0
GIEN
NINT
All Interrupt flags (in IFR) except ESPI can be masked in the global interrupt enable register (GIEN). An Interrupt will be signalled by NINT going low until either the corresponding mask or the flag itself will be reset by the application software. An autoreset function is available for IFR, allowing to remove all interrupt flags after reading their state (see SPI).
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4 REMARKS FOR APPLICATION
Figure 28. General circuit connection diagram
VS
Thermal Supervision
V2
*
10u 47n Standby Supply & Adjustable RC-Oscillator V1 120K Programmable Timer NRES
*
47n 10u
Peripheral Supply
*
47n 10u opt
NINT Wakeup & Interrupt Detection WAKE SCLK SIN SOUT C
V3 33u
SPI
*
47n RTH CAN Transceiver Groundshift Detection
RX
*
47p
TX
CANH CANL
*
47p RTL ID-Filter GND
99AT0032
C* ceramic C close to pin recommended for EMI
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mm DIM. MIN. A A1 B C D E e H h L K 10 0.25 0.4 2.35 0.1 0.33 0.23 12.6 7.4 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.3 0.51 0.32 13 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291
inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.050 0.419 0.030 0.050
OUTLINE AND MECHANICAL DATA
SO20
0 (min.)8 (max.)
L
h x 45
A B e K H D A1 C
20
11 E
1
0 1
SO20MEC
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mm MIN. 0.1 0 0.4 0.23 15.8 9.4 13.9 1.27 11.43 10.9 5.8 0 15.5 0.8 11.1 2.9 6.2 0.1 15.9 1.1 1.1 0.031 8 (typ.) 8 (max.) 10 0.394 0.228 0.000 0.610 0.429 TYP. MAX. 3.6 0.3 3.3 0.1 0.53 0.32 16 9.8 14.5 0.000 0.016 0.009 0.622 0.370 0.547 0.050 0.450 0.437 0.114 0.244 0.004 0.626 0.043 0.043 JEDEC MO-166 0.004 MIN. inch TYP. MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570
Weight: 1.9gr
DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 G H h L N S T
OUTLINE AND MECHANICAL DATA
(1) "D and E1" do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006") - Critical dimensions: "E", "G" and "a3".
PowerSO20
N
N a2 b e A
R
c DETAIL B a1 E DETAIL A
DETAIL A e3 H
lead
D a3 DETAIL B
20 11
Gage Plane 0.35
slug
-C-
S E2 T E1 BOTTOM VIEW
L
SEATING PLANE G C
(COPLANARITY)
E3
1 10
h x 45
PSO20MEC
D1
0056635
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L4969
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